A sample and hold circuit is a circuit that monitors a signal and provides a constant value at predetermined times. A block diagram of one such sample and hold circuit 10 is shown in FIG. 1. This circuit 10 includes a switch 12 coupled in series with a capacitor 14. In operation, the switch 12 is closed at the sample rate and the voltage across the hold capacitor 14 represents a first order held version of the input waveform V.sub.in. In CMOS technologies, this circuit is realized as a combination of MOS transistors.
FIG. 2a shows the schematic of an elementary NMOS sample and hold circuit 20. In this implementation, switch 12 is an NMOS transistor 12. The operation of a PMOS transistor is analogous and will not be discussed here. FIG. 2b shows a timing diagram for a pulse .phi.1 that is applied to the gate of transistor 12. When the gating waveform .phi.1 goes high (V.sub.DD), the switch 12 is on and the capacitor 14 is shorted to the input. When the input goes low (zero), the switch is off. As a result, the value of the input voltage V.sub.in will be held on the hold capacitor 14.
While having the benefit of being simple in construction, the circuit of FIG. 2a has a number of disadvantages. When the switch 12 is turned off, a part of the charge in the channel of the NMOS transistor 12 is dumped on to the hold capacitor 14. Since this charge is signal dependent and nonlinear, this will cause distortion. In addition, the ON resistance of the switch 12 is signal dependent thereby causing further distortion. Also, the exact sampling instant of the switch is that time at which the gate-source voltage of the switch V.sub.GS is about equal to the transistor's threshold voltage V.sub.T. Since V.sub.GS =V.sub.DD -V.sub.IN, it is clear that the sampling instant is signal dependent. This too will cause significant distortion.
To mitigate some of the problems of the single channel MOS switch discussed above, bootstrapped switches have been proposed. The idea behind bootstrapping is to keep the gate source drive of the switch constant. This is done as shown in FIG. 3, which includes FIGS. 3a and 3b.
Referring first to FIG. 3a, the circuit 30 includes a sample switch 12, comprising an NMOS transistor, and a hold capacitor 14. In this case, however, the gate of transistor 12 is coupled to a bootstrap circuit that includes bootstrap capacitor 32 and switches 34-37. FIG. 3b shows the timing of the waveforms .phi.1 and .phi.2.
During the first phase, when .phi.1 is high, bootstrap capacitor 32 is charged to a bias voltage V.sub.BIAS. During the second phase, when .phi.2 is high, the bootstrap capacitor 32 is put across the gate and source terminals of switch 12. This ensures that the V.sub.GS of the MOSFET is held constant at V.sub.BIAS irrespective of the input voltage Vet.
The channel charge is given by Q.sub.ch =C.sub.ox (V.sub.BIAS -V.sub.T (V.sub.IN)), where C.sub.ox is the capacitance across the gate oxide of transistor 12 and V.sub.T is the threshold voltage of transistor 12, the voltage being a function of the input voltage V.sub.IN. From this relationship, it is thus seen that the inversion charge is substantially independent of the input voltage, except for a second order dependence through the threshold voltage.
This circuit, while exhibiting good performance, has a problem when implemented in an n-well technology. The channel charge Q.sub.ch, and thus the switch 12 resistance, depend on the input voltage V.sub.IN through the threshold V.sub.T. Accordingly, distortion will result.
This problem is solved by a modified arrangement proposed by Pan et al., "A 3.3V, 12b, 50 MSample/s A/D Converter in 0.6 .mu.m CMOS with over 80 dB SFDR," IEEE International Solid State Circuit Conference, Feb. 2000, pp. 40-41. FIG. 4a illustrates such a circuit 40 and FIG. 4b shows the corresponding waveforms.
The circuit 40 includes a sample switch 12, comprising an NMOS transistor, and a hold capacitor 14. The gate of transistor is coupled to switch 42, which goes to ground, and switch 44, 16 which goes to a voltage source V.sub.bat. In this arrangement, V.sub.bat is implemented as a switched capacitor level shifter. Transistor 46 is a replica of the switch device 12. Operational amplifier 48 is coupled between V.sub.bat and the drain of replica transistor 46. Current source 50 maintains a constant current through the transistor 46.
In operation, replica transistor 46 operates in saturation. The gate of this transistor could exceed the supply voltage V.sub.dd. It is easily seen that if the operational amplifier is ideal, the potential at the gate of transistor 46 is given by V.sub.IN +V.sub.T (V.sub.IN +V.sub.a, and the channel charge is Q.sub.ch =C.sub.ox (V.sub.a), where V.sub.a is a constant voltage based on the VGS-VT of transistor 46, which is dependent primarily on the current generated by current source 50. Advantageously, the channel charge Q.sub.ch is independent of the input voltage V.sub.IN and body effect.
The circuit does, however, have a number of disadvantages. Transistor 46 operates in saturation while transistor 12 operates in the triode region. Thus, their respective threshold voltages may not be equal, especially in short channel technologies. Further, the transistor 46 is subject to large variations in drain source voltages. In short channel CMOS, this is a serious problem because of the modification of the threshold of transistor 46 through drain induced barrier lowering (DIBL). Finally, the operational amplifier 48 tends to consume a lot of power if fast settling is required. Incomplete settling of the operational amplifier reduces performance.